The present invention relates to a signal processing device and a D/A converter, and more particularly to a D/A conversion technique used in a signal processing device including an analog-digital mixed loop having a digital section and an analog section for converging a loop output to a target value through the analog-digital mixed loop.
FIG. 14 illustrates a configuration of a reproduction signal processing device as an example of a signal processing device having an analog-digital mixed loop. A pickup 1 reads out information recorded on a recording medium 3 such as an optical disk or a magnetic disk that is rotated by a spindle motor 2, and outputs the information as a reproduction signal to a variable-gain amplifier 4. The amplitude of the reproduction signal is adjusted by the variable-gain amplifier 4 to be in conformity with the input dynamic range of an A/D converter 6. After the noise of the signal in high-frequency band is eliminated through an analog filter 5, the signal is quantized by the A/D converter 6 into a digital signal DT0.
The digital signal DT0 is input to a digital signal processing block 7 and a PLL block 8, which extract recorded data DT1 and a clock CK1, respectively, from the digital signal DT0. Moreover, the digital signal DT0 is fed back to the analog section through an offset adjustment block 9 and a gain adjustment block 10. The offset adjustment block 9 produces an analog control signal based on the digital signal DT0 so as to correct the offset of the A/D converter 6. The gain adjustment block 10 produces an analog control signal based on the digital signal DT0 so as to correct the gain factor of the variable-gain amplifier 4.
There is an analog-digital mixed loop also in the PLL block 8. FIG. 15 illustrates an internal configuration of the PLL block 8. While the PLL block 8 is in the frequency detection mode, a frequency comparator 82 calculates the frequency error between a fed-back signal (a signal obtained by dividing the frequency of the output clock CK1 by a frequency divider 89) and the digital signal DT0. A loop filter 84 produces a digital control signal DT11 based on the error amount. Then, the digital control signal DT11 is converted into an analog control signal DT12 by a D/A converter 86. A VCO (Voltage Controlled Oscillator) 88 outputs a corrected clock CK1 based on the analog control signal DT12.
A current-cell type D/A converter, which is capable of operating at a high speed and has a high resolution, is used as the D/A converter 86 in the PLL block 8.
FIG. 16 illustrates an internal configuration of the current-cell type 8-bit D/A converter 86. The received 8-bit digital control signal DT11 is stored in a register section 861 in synchronization with the system clock. Then, the lower four bits are used for turning ON/OFF a group of weighted current sources 863, while the upper four bits are decoded into 15-bit data by a decoder section 862. The 15-bit data is used for turning ON/OFF a number of current cells (16I0) in a current cell matrix 864 based on the value of the upper four bits.
Assume a case where xe2x80x9c00101100xe2x80x9d is input, as the digital control signal DT11, to the D/A converter 86. In this case, since the lower four bits are xe2x80x9c1100xe2x80x9d, the output of the group of weighted current sources 863 is 8I0+4I0=12I0. Moreover, since the upper four bits are xe2x80x9c0010xe2x80x9d, two current cells of the current cell matrix 864 are turned ON to give an output of 16Io*232=I0. The output from the group of weighted current sources 863 and that from the current cell matrix 864 are added together by an output section 865, which outputs 12I0+32I0=44I0 as the analog control signal DT12.
In the PLL block 8, the output frequency range of the VCO 88, which is to be controlled, is quite wide. Therefore, a D/A converter having a high resolution is used as each of D/A converters 85 and 86. However, a D/A converter having a high resolution takes, as its input, the digital control signal DT11 having a large bit width, whereby the bit width for the internal operation becomes large. Thus, such D/A converters, particularly those of a current-cell type, lead to an increase in the circuit area and make it difficult to reduce the cost.
Moreover, not only the PLL block 8, but in general, a signal processing device having an analog-digital mixed loop requires a D/A converter or a similar element. If the signal processing device requires a D/A converter or a similar element having a high resolution, there will be problems as those described above.
The present invention has been made in view of the above, and has an object to provide a D/A converter in an analog-digital mixed loop with a reduced circuit area without sacrificing the resolution. It is also an object of the present invention to provide a signal processing device including such a D/A converter.
In order to achieve the objects set forth above, the present invention provides a signal processing device including a loop having a digital section for processing a digital signal and an analog section for processing an analog signal for converging a loop output to a target value through the loop, the signal processing device including a D/A converter for converting an m-bit (m is a positive integer) digital control signal received from the digital section into an analog control signal having substantially the same precision as that of the m-bit digital control signal so as to output the analog control signal to the analog section. The D/A converter includes: a bit modulation section for modulating the m-bit digital control signal into an n-bit (n is a positive integer: n less than m) intermediate digital signal whose temporal average precision is substantially the same as the precision of the m-bit digital control signal; a D/A conversion section for converting the n-bit intermediate digital signal into an intermediate analog signal having a range corresponding to m bits; and an analog filter for smoothing the intermediate analog signal so as to output the smoothed signal as the analog control signal.
According to the present invention, the m-bit digital control signal is modulated by the bit modulation section into the intermediate digital signal while reducing the bit width from m bits to n bits. The temporal average precision of the intermediate digital signal is substantially the same as the precision of the m-bit digital control signal. Then, the intermediate digital signal is converted by the D/A conversion section into the intermediate analog signal having a range corresponding to m bits. As the intermediate digital signal, the intermediate analog signal also has a substantially m-bit precision. Finally, the intermediate analog signal is smoothed through the analog filter so as to be output as the analog control signal having substantially the same precision as the m-bit digital control signal. Therefore, according to the present invention, it is possible to reduce the bit width used for the operation inside the D/A converter, thereby reducing the circuit area of the signal processing device as a whole without sacrificing the resolution of the D/A converter.
It is preferred that the bit modulation section produces, from lower (mxe2x88x92n) bit/bits of the m-bit digital control signal, a 1-bit modulation bit whose temporal average precision is substantially the same as an (mxe2x88x92n)-bit precision so as to produce the n-bit intermediate digital signal by adding together upper n bit/bits of the m-bit digital control signal and the modulation bit.
In order to achieve the objects set forth above, the present invention also provides a signal processing device including a loop having a digital section for processing a digital signal and an analog section for processing an analog signal for converging a loop output to a target value through the loop, the signal processing device including a D/A converter for converting an m-bit (m is a positive integer) digital control signal received from the digital section into an analog control signal having substantially the same precision as that of the m-bit digital control signal so as to output the analog control signal to the analog section, the D/A converter including: a bit modulation section for producing, from lower (mxe2x88x92n) bit/bits (n is a positive integer: n less than m) of the m-bit digital control signal, a 1-bit modulation bit whose temporal average precision is substantially the same as an (mxe2x88x92n)-bit precision; a D/A conversion section for converting upper n bit/bits of the m-bit digital control signal into a first intermediate analog signal having a range corresponding to m bits; a power supply section, which is capable of outputting an analog value corresponding to one bit in the D/A conversion section, and which outputs a second intermediate analog signal in response to the modulation bit as a switching signal; an adder for adding together the first and second intermediate analog signals; and an analog filter for smoothing an output from the adder so as to output the smoothed signal as the analog control signal.
According to the present invention, the bit modulation section produces the one-bit modulation bit from the lower (mxe2x88x92n) bit/bits of the m-bit digital control signal. The temporal average precision of the modulation bit is substantially (mxe2x88x92n) bit/bits. The modulation bit is used in the power supply section as the switching signal, whereby the second intermediate analog signal is output. The precision of the second intermediate analog signal is also substantially (mxe2x88x92n) bit/bits, as that of the modulation bit. The second analog signal is added together with the first intermediate analog signal, which is obtained by conversion through the D/A conversion section, to produce a signal whose precision is substantially m bits. Finally, the output from the adder is smoothed through the analog filter, and the smoothed signal is output as the analog control signal having substantially the same precision as that of the m-bit digital control signal. Therefore, according to the present invention, it is possible to reduce the bit width used for the operation inside the D/A converter, thereby reducing the circuit area of the signal processing device as a whole without sacrificing the resolution of the D/A converter.
It is preferred that the bit modulation section produces the modulation bit in synchronization with a second operating clock that is faster than a first operating clock, the first operating clock being an operating clock of the D/A conversion section.
In this way, the modulation bit is produced in synchronization with the second operating clock being faster than the first operating clock, which is the operating clock of the D/A conversion section. Thus, the input signal to the analog filter is smoothed more quickly, and the loop output of the signal processing device can be converged to the target value more quickly.
It is preferred that the bit modulation section produces, as the modulation bit, a fixed value at one logical level if a value of the lower (mxe2x88x92n) bit/bits of the m-bit digital control signal is equal to a predetermined reference value, whereas the bit modulation section produces, as the modulation bit, a fluctuating value in which a number of bits corresponding to the value of the lower (mxe2x88x92n) bit/bits of the m-bit digital control signal are at the other logical level for consecutive 2(mxe2x88x92n) occurrences of the modulation bit if the value of the lower (mxe2x88x92n) bit/bits of the m-bit digital control signal is not equal to the predetermined reference value.
Thus, if the value of the lower (mxe2x88x92n) bit/bits of the digital control signal is equal to the predetermined reference value (e.g., xe2x80x9c0xe2x80x9d), the modulation bit is a fixed value at one logical level (e.g., xe2x80x9c0xe2x80x9d). If the value of the lower (mxe2x88x92n) bit/bits of the digital control signal is not equal to the predetermined reference value, the modulation bit is a fluctuating value in which a number of bits corresponding to the value of the lower (mxe2x88x92n) bit/bits of the m-bit digital control signal are at the other logical level (e.g., xe2x80x9c1xe2x80x9d) for consecutive 2(mxe2x88x92n) occurrences of the modulation bit. The fluctuating value, when the temporal average thereof is taken, can represent an intermediate value between xe2x80x9c0xe2x80x9d and xe2x80x9c1xe2x80x9d. For example, when the value of the lower two bits is xe2x80x9c3xe2x80x9d, the fluctuating value is xe2x80x9c01110111 . . . xe2x80x9d, and when the value is xe2x80x9c2xe2x80x9d, the fluctuating value is xe2x80x9c01010101 . . . . .xe2x80x9d. In these cases, the temporal average of the fluctuating value is xe2x80x9c0.75xe2x80x9d and xe2x80x9c0.5xe2x80x9d, respectively, indicating that the 1-bit modulation bit can represent a value of a substantially higher precision (a precision corresponding to two bits). Thus, according to the present invention, the fluctuating value is used, whereby the temporal average precision of the modulation bit can be substantially the same as an (mxe2x88x92n)-bit precision.
It is more preferred that: n=mxe2x88x921; and the bit modulation section produces, as the modulation bit, a fixed value xe2x80x9c0xe2x80x9d if a lower one bit of the m-bit digital control signal is xe2x80x9c0xe2x80x9d, whereas the bit modulation section produces, as the modulation bit, a fluctuating value that alternately takes xe2x80x9c0xe2x80x9d and xe2x80x9c1xe2x80x9d if the lower one bit of the m-bit digital control signal is xe2x80x9c1xe2x80x9d.
It is preferred that: the m-bit digital control signal is modulated so that a temporal average precision thereof is substantially higher than m bits; and the bit modulation section produces the modulation bit so that the temporal average precision of the modulation bit and a temporal average precision of the lower (mxe2x88x92n) bit/bits of the m-bit digital control signal are substantially the same.
In this way, in a case where the m-bit digital control signal, which is input to the D/A converter, is modulated so that the temporal average precision thereof is increased to be substantially higher than m bits (for example, in the case of a variable value), the modulation bit is produced so that the precision thereof is substantially the same as the increased precision. Thus, the resolution of the D/A converter can be increased according to the precision of the input digital control signal.
It is more preferred that: n=mxe2x88x921; and the bit modulation section produces, as the modulation bit, a fluctuating value that takes xe2x80x9c1xe2x80x9d when a lower one bit of the m-bit digital control signal takes xe2x80x9c1xe2x80x9d twice.
It is preferred that the analog filter changes a cut-off frequency for the analog control signal according to an operating clock of the signal processing device.
In order to achieve the objects set forth above, the present invention also provides a D/A converter, including: a bit modulation section for modulating an m-bit (m is a positive integer) digital signal into n-bit (n is a positive integer: n less than m) intermediate digital signal whose temporal average precision is substantially the same as a precision of the m-bit digital signal; a D/A conversion section for converting the n-bit intermediate digital signal into an intermediate analog signal having a range corresponding to m bits; and an analog filter for smoothing the intermediate analog signal so as to output the smoothed signal as an analog signal whose precision is substantially the same as that of the m-bit digital signal.
It is preferred that the bit modulation section produces, from lower (mxe2x88x92n) bit/bits of the m-bit digital signal, a 1-bit modulation bit whose temporal average precision is substantially the same as an (mxe2x88x92n)-bit precision so as to produce the n-bit intermediate digital signal by adding together upper n bit/bits of the m-bit digital signal and the modulation bit.
In order to achieve the objects set forth above, the present invention also provides a D/A converter, including: a bit modulation section for producing, from lower (mxe2x88x92n) bit/bits (m and n are each a positive integer: n less than m) of an m-bit digital signal, a 1-bit modulation bit whose temporal average precision is substantially the same as an (mxe2x88x92n)-bit precision; a D/A conversion section for converting upper n bit/bits of the m-bit digital signal into a first intermediate analog signal having a range corresponding to m bits; a power supply section, which is capable of outputting an analog value corresponding to one bit in the D/A conversion section, and which outputs a second intermediate analog signal in response to the modulation bit as a switching signal; an adder for adding together the first and second intermediate analog signals; and an analog filter for smoothing an output from the adder so as to output the smoothed signal as an analog signal whose precision is substantially the same as that of the m-bit digital signal.
It is preferred that: the m-bit digital signal is modulated so that a temporal average precision thereof is substantially higher than m bits; and the bit modulation section produces the modulation bit so that the temporal average precision of the modulation bit and a temporal average precision of the lower (mxe2x88x92n) bit/bits of the m-bit digital signal are substantially the same.